1. Field of the Invention
The present invention relates to a semiconductor memory device which rewritably stores data in a plurality of memory cells formed at intersections of a plurality of word lines and a plurality of bit lines, and particularly relates to a semiconductor memory device employing an embedded bit line structure which is located below a vertical type transistor formed in each memory cell.
2. Description of the Related Art
Generally, a memory cell array of a DRAM includes a large number of memory cells formed at intersections of bit lines and word lines. In recent years, attention is paid to a technique using a vertical type transistor as a memory cell structure of the DRAM (e.g., see Patent References 1 and 2). In order to form a fine memory cell with a design rule such as 4F2, it is advantageous for integration and manufacturing to configure the memory cell array using vertical type transistors. On the premise of the structure of the vertical type transistor, it is general that a capacitor of each memory cell is formed over the vertical type transistor and that an embedded bit line structure in which a bit line is arranged below the vertical type transistor is employed.
Patent Reference 1: Laid-open Japanese Patent Publication No. 2002-94027
Patent Reference 2: Japanese Patent No 3745392
However, if the embedded bit line structure is employed, it is difficult to form a bit line arranged in a lower layer using metal or silicide having a low resistance. Therefore, the bit line needs to be formed using polysilicon or a diffusion layer, which inevitably causes the resistance thereof to increase, and it arises a problem of a decrease in operation speed of the DRAM. Meanwhile, the above Patent Reference 1 discloses a structure in which a lower source/drain electrode of the vertical type transistor is withdrawn upward via a contact and is connected to a bit line formed using a tungsten film. Thereby, a bit line resistance can be suppressed, but a complex structure is required for withdrawing the bit line upward, and it is undesirable in terms of an increase in the number of manufacturing steps and an increase in cost. Further, the above Patent Reference 2 discloses a structure in which a bit line is formed by doping n+ impurity into a polysilicon layer formed on a silicon oxide film. Thereby, a bit line capacitance can be reduced relative to a case of forming the bit line using an n+ impurity diffusion layer formed in a p type substrate. However, the bit line resistance becomes larger than that in a case of using the metal or silicide, and it is a problem that the operation speed further decreases. In this manner, when the memory cell array is configured by employing the vertical type transistor and the embedded bit line structure, it is difficult to prevent a decrease in the operation speed caused by an increase in the bit line resistance without deterioration of manufacturing and cost.